Fahad Rahman Amik
Mila McGill Mila - Quebec AI Institute and McGill University

I am a PhD Student in Electrical & Computer Engineering at Mila - Quebec AI Institute and McGill University, working with Prof. Boris Vaisband and Prof. Warren Gross. My research focuses on Machine Learning for Electronic Design Automation (ML for EDA), with particular interests in Graph Representation Learning, Timing Analysis, and Physical Design.

Fahad Rahman Amik
fahad.amik (at) mail.mcgill.ca Google Scholar LinkedIn GitHub CV
Education
  • McGill University
    Mila - Quebec AI Institute and McGill University
    PhD Student in Electrical & Computer Engineering
    Topic: Machine Learning for Electronic Design Automation
    Jan. 2023 - Present
  • North South University
    North South University
    Bachelor of Science in Computer Science & Engineering
    May 2017 - April 2021
Experience
  • Huawei Technologies
    Noah's Ark Lab
    Montreal, Canada
    Associate ML Researcher, Intern
    Graph Representation Learning for Performance Prediction
    Dec. 2024 - June 2025
  • Huawei Technologies
    Noah's Ark Lab
    Montreal, Canada
    Associate ML Researcher, Intern
    Reinforcement Learning and Graph Neural Networks for Analog Transistor Sizing
    May 2023 - Oct. 2023
  • Hilinkz Ltd.
    Hilinkz Ltd.
    Dhaka, Bangladesh
    Chief Executive Officer
    Led team, designed architecture, developed web applications
    Feb. 2021 - Dec. 2022
  • HURU Technologies
    HURU Technologies Ltd.
    Dhaka, Bangladesh
    Software Engineer Intern
    Developed web app for Digital Service Hiring Solution
    Oct. 2020 - Jan. 2021
Honors & Awards
  • DAC Young Fellow
    2025
  • MEDA Award - McGill Engineering Doctoral Award
    2023
  • 50% Merit-based Tuition Waiver, North South University
    2017
Research Interests
  • Graph Representation Learning
  • Electronic Design Automation
  • Timing Analysis
  • Physical Design
  • Machine Learning for EDA
Selected Publications
Graph-Based Timing Prediction ASPDAC
Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model

F.R. Amik, Y. Safari, Z. Zhang, B. Vaisband

Asia and South Pacific Design Automation Conference (ASPDAC) 2025

Developed an RTL dataset generator and utilized LLemma-7B to generate embeddings for graph-based timing prediction at early-stage RTL design.

Graph-Based Timing Prediction ASPDAC
Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model

F.R. Amik, Y. Safari, Z. Zhang, B. Vaisband

Asia and South Pacific Design Automation Conference (ASPDAC) 2025

Developed an RTL dataset generator and utilized LLemma-7B to generate embeddings for graph-based timing prediction at early-stage RTL design.

Generalizable Netlist Representation GLSVLSI
Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design

S. Penmetsa, F.R. Amik, Z. Zhang, et al.

34th Great Lakes Symposium on VLSI (GLSVLSI) 2024

Proposed a novel heterogeneous graph representation for analog circuits with enhanced generalization and knowledge transferability.

Generalizable Netlist Representation GLSVLSI
Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design

S. Penmetsa, F.R. Amik, Z. Zhang, et al.

34th Great Lakes Symposium on VLSI (GLSVLSI) 2024

Proposed a novel heterogeneous graph representation for analog circuits with enhanced generalization and knowledge transferability.